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MITSUBISHI
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
DESCRIPTION
The M66287FP is a high-speed field memory with three FIFO (First In First Out) memories of 262144-word x 8-bit configuration (2M bits) which uses high-performance silicon gate CMOS process technology. One of three FIFO memories consists of two FIFO memories of 262144-word x 4-bit (1M bits). Five types of operation can be performed through the following mode settings: Mode1 : 3-system delay data output by 3-system individual input of 256K-word x 8-bit FIFO Mode2 : Simultaneous output of 1 to 3-line delay data by 1-system input of 256K-word x 8-bit FIFO Mode3 : Simultaneous output of 1 to 2-line delay data by 1-system input of 256K-word x 8-bit FIFO and,1-system delay data output by 1-system input of 256K-word x 8-bit FIFO Mode4 : 2-system delay data output by 2-system individual input of 256K-word x 12-bit FIFO Mode5 : Simultaneous output of 1 to 2-line delay data by 1-system input of 256K-word x 12-bit FIFO The above-mentioned function is most suitable for image data correction across multiple fields. Because three pieces of 2M-bit FIFO are contained in one chip, a low power consumption of a set can be realized.
FEATURES
Memory configuration The total memory capacity is 6M bits (static memory). The following two types of memory configurations can be selected. 262144-word x 8-bit x 3-line configuration 262144-word x 12-bit x 2-line configuration 16.6 ns (Min.) 13.0 ns (Max.) 2.0 ns (Min.) Internal = 1.8 V 0.18 V I/O = 3.3 V 0.3 V
High - speed cycle High - speed access Output hold Supply voltage
Variable length delay bit Five modes can be selected Write and read function can be operated completely independently and asynchronously Output 3 states Package 100pin QFP (100P6Q-A)
APPLICATION
W-CDMA base station, Digital PPC, Digital television, VTR and so on.
MODE DESCRIPTIONS DRAWING
MODE 1
8 DA<7:0> WCKA WRESA WEA 8 DB<7:0> WCKB WRESB WEB 8 DC<7:0> WCKC WRESC WEC 256K x 8-bit FIFO 256K x 8-bit FIFO 8 QB<7:0> RCKB RRESB REB 8 QC<7:0> RCKC RRESC REC 8 256K x 8-bit FIFO 8 QC<7:0> DC<7:0> WCKC WRESC WEC 8 256K x 8-bit FIFO 8 QC<7:0> RCKC RRESC REC 8 256K x 8-bit FIFO 8 QB<7:0> 8 256K x 8-bit FIFO 8 QB<7:0> 12 DB<11:0> WCKB WRESB WEB 256K x 12-bit FIFO 12 QB<11:0> RCKB RRESB REB
12 256K x 12-bit FIFO 12 QB<11:0>
2M-bit x 3 configuration 8-bit bus I/F MODE 2
8 QA<7:0> RCKA RRESA REA DA<7:0> WCKA WRESA WEA 256K x 8-bit FIFO 8 QA<7:0> RCKA RRESA REA DA<7:0> WCKA WRESA WEA
MODE 3
8 256K x 8-bit FIFO 8 QA<7:0> RCKA RRESA REA DA<11:0> WCKA WRESA WEA
3M-bit x 2 configuration 12-bit bus I/F MODE 4 MODE 5
12 256K x 12-bit FIFO 12 QA<11:0> RCKA RRESA REA
12 DA<11:0> WCKA WRESA WEA 256K x 12-bit FIFO 12 QA<11:0> RCKA RRESA REA
8 256K x 8-bit FIFO
The three pieces of 256Kword x 8-bit FIFO can be operated completely independently.
The three pieces of 256Kword x 8-bit FIFO are cascade-connected. Write and read operation of FIFO after the 2nd line is controlled by the read system pin of the 1st line.
The two pieces of 256Kword x 8-bit FIFO are cascade-connected and, a piece of 256K-word x 8-bit FIFO can be operated completely independently. Write and read operation of FIFO at the 2nd line is controlled by the read system pin of the 1st line.
The two pieces of 256Kword x 12-bit FIFO can be operated completely independently.
The two pieces of 256Kword x 12-bit FIFO are cascade-connected. Write and read operation of FIFO at the 2nd line is controlled by the read system pin of the 1st line.
Note: Please refer to "Pin Assignment Table" in "MODE 4 and MODE 5 OPERATION DESCRIPTIONS" for assignment of external pins, Dx<11:0> and Qx<11:0> when used in 12-bit bus interface. (c) 2002 MITSUBISHI ELECTRIC CORPORATION 1
MITSUBISHI
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
PIN CONFIGURATION (TOP VIEW)
TEST1 VCC18 GND DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 VCCIO GND QA7 QA6 QA5 QA4 QA3 QA2 QA1 QA0 VCC18 GND VCCIO
99 98 97 96 95 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 94 77 76
TEST3 WCKA WRESA WEA VCCIO GND WCKB WRESB WEB VCCIO GND WCKC WRESC WEC VCC18 GND DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 VCCIO
1 2 3 4 5 6 7 8 9 68 67 66 65 64 63 62 61 60 59 58 19 57 20 56 21 55 22 23 24 25 54 53 52 51 26 27 28 29 30 31 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 32 50 72 71 70 69 75 74 73
100
TEST2
GND RCKA RRESA REA VCCIO GND RCKB RRESB REB MODE1 MODE2 MODE3 RCKC RRESC REC VCCIO GND QB7 QB6 QB5 QB4 QB3 QB2 QB1 QB0
M66287FP
10 11 12 13 14 15 16 17 18
(c) 2002 MITSUBISHI ELECTRIC CORPORATION
GND VCC18 GND DC0 DC1 DC2 DC3 DC4 DC5 DC6 DC7 VCCIO GND QC0 QC1 QC2 QC3 QC4 QC5 QC6 QC7 VCCIO GND VCC18 GND
Outline 100P6Q-A
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MITSUBISHI
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
BLOCK DIAGRAM
Data input DA<7:0>
DB<7:0>
DC<7:0>
INPUT BUFFER
Mode setting input MODE<3:1> Write control inputs for A-system WRITE CONTROL CIRCUIT READ CONTROL CIRCUIT WCKA WRESA WEA Write control inputs for B-system WCKB WRESB WEB Write control inputs for C-system WCKC WRESC WEC Test setting input TEST<3:1>
MODE CONTROL CIRCUIT
Read control inputs for A-system RCKA RRESA REA Read control inputs for B-system RCKB RRESB REB Read control inputs for C-system RCKC RRESC REC
WRITE ADDRESS COUNTER
MEMORY ARRAY
256K-WORD x 8-BIT 256K-WORD x 4-BIT 256K-WORD x 4-BIT 256K-WORD x 8-BIT READ ADDRESS COUNTER
MODE CONTROL CIRCUIT
VCC 18
OUTPUT BUFFER
VCC IO GND
GND Data output
QA<7:0> QB<7:0> QC<7:0>
(c) 2002 MITSUBISHI ELECTRIC CORPORATION
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MITSUBISHI
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
PIN FUNCTION DESCRIPTIONS
Pin name WCKA WCKB WCKC WEA WEB WEC WRESA WRESB WRESC Name Write clock input Input / output Input Function They are write clock inputs. WCKA is a write clock for the A-system, WCKB for the B-system and WCKC for the C-system. They are write enable control inputs. When they are "L", a write enable status is provided. WEA is a write enable for the A-system, WEB for the B-system and WEC for the C-system. They are reset inputs to initialize a write address counter of internal FIFO. When they are "L", a write reset status is provided. WRESA is a write reset for the A-system, WRESB for the B-system and WRESC for the C-system. They are read clock inputs. RCKA is a read clock for the A-system, RCKB for the B-system and RCKC for the C-system. They are read enable control inputs. When they are "L", a read enable status is provided. REA is a read enable for the A-system, REB for the B-system and REC for the C-system. They are reset inputs to initialize a read address counter of internal FIFO. When they are "L", a read reset status is provided. RRESA is a read reset for the A-system, RRESB for the B-system and RRESC for the C-system. They are 8-bit data input bus. DA<7:0> is a data input bus for the A-system, DB<7:0> for the Bsystem and DC<7:0> for the C-system. They are 8-bit data output bus. QA<7:0> is a data output bus for the A-system, QB<7:0> for the Bsystem and QC<7:0> for the C-system. They are pins for setting operation mode. Setting is refer to MODE SET-table. They are pins for test. Setting of TEST1 depends on the rising time of the 1.8 V system power supply. For further details, refer to page 11. TEST2 and TEST3 should be fixed at "L". This is a 3.3 V power supply pin for I/O. This is a 1.8 V power supply pin for internal circuit. This is a ground pin.
Write enable input
Input
Write reset input
Input
RCKA RCKB RCKC REA REB REC RRESA RRESB RRESC
Read clock input
Input
Read enable input
Input
Read reset input
Input
DA<7:0> DB<7:0> DC<7:0> QA<7:0> QB<7:0> QC<7:0> MODE<3:1> TEST<3:1>
Data input
Input
Data output
Output
Mode setting input Test setting input
Input Input
VCCIO VCC18 GND
Power supply pin for I/O Power supply pin for internal circuit Ground pin
-
(c) 2002 MITSUBISHI ELECTRIC CORPORATION
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MITSUBISHI
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
MODE SET
MODE<3:1> should be set to "L" or "H" as shown below according to the five modes to be used. MODE 3 L L L L H MODE 2 L L H H L other than those above MODE 1 L H L H L Operation mode MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 1
MODE 1 OPERATION DESCRIPTIONS

DA<7:0> WCKA WRESA WEA
8 8
256K x 8-bit FIFO(A)
QA<7:0> RCKA RRESA REA
In mode 1, three FIFO memories with 8-bit data bus can be controlled completely individually. Taking FIFO (A) as an example, the operation of FIFO memory is described below. The operation of FIFO (B) and FIFO (C) are the same as that of FIFO (A).
8
8
DB<7:0> WCKB WRESB WEB
256K x 8-bit FIFO(B)
QB<7:0> RCKB RRESB REB
When write enable input WEA is "L", the contents of data input DA<7:0> are written into FIFO (A) in synchronization with the rising of write clock input WCKA. At this time, the write address counter of FIFO (A) is incremented. When WEA is "H", writing into FIFO (A) is disabled and the write address counter
8
8
DC<7:0> WCKC WRESC WEC
256K x 8-bit FIFO(C)
QC<7:0> RCKC RRESC REC
of FIFO (A) is stopped. When write reset input WRESA is "L", the write address counter of FIFO (A) is initialized.
When read enable input REA is "L", the contents of FIFO (A) are outputted to data output QA<7:0> in synchronization with the rising of read clock input RCKA. At this time, the read address counter of FIFO (A) is incremented. When REA is "H", reading from FIFO (A) is disabled and the read address counter of FIFO (A) is stopped. Also QA<7:0> become high impedance state. When read reset input RRESA is "L", the read address counter of FIFO (A) is initialized. Note : The three pieces of 256K-word x 8-bit FIFO can be operated completely independently.
(c) 2002 MITSUBISHI ELECTRIC CORPORATION
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MITSUBISHI
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
MODE 2 OPERATION DESCRIPTIONS

DA<7:0> WCKA WRESA WEA
8 8
256K x 8-bit FIFO(A)
QA<7:0> RCKA RRESA REA
In mode 2, three FIFO memories with 8-bit data bus are cascade-connected and it is possible to generate delay data for 3-lines without external wiring. When write enable input WEA is "L", the contents of data input DA<7:0> are written into FIFO (A) in synchronization with the rising of write clock input
8
8
256K x 8-bit FIFO(B)
QB<7:0>
WCKA. At this time, the write address counter of FIFO (A) is incremented. When WEA is "H", writing into FIFO (A) is disabled and the write address counter of FIFO (A) is stopped. When write reset input WRESA is "L", the write address counter of FIFO (A) is initialized.
8
8
256K x 8-bit FIFO(C)
QC<7:0>
When read enable input REA is "L", the contents of FIFO (A), FIFO (B) and FIFO (C) are outputted to each QA<7:0>, QB<7:0>, QC<7:0> in synchronization with the rising of read clock input RCKA. At this time, the read address counters of all FIFOs are incremented.
Also the data of the upper FIFO is written into the lower FIFO in synchronization with the rising of RCKA. At this time, the write address counters of FIFO (B) and FIFO (C) are incremented simultaneously. When REA is "H", reading from FIFO (A), FIFO (B) and FIFO (C) is disabled and the read address counter of each FIFO is stopped. Also all data outputs become high impedance state. And writing into FIFO (B) and FIFO (C) is disabled and the write address counters of FIFO (B) and FIFO (C) are stopped. When read reset input RRESA is "L", the read address counter of FIFO (A) and the write address counters/read address counters of FIFO (B) and FIFO (C) are initialized. And, in mode 2, all pins for the A-system, QB<7:0> and QC<7:0> are only used. Therefore the write/read control pins for the B-system and C-sytsem, DB<7:0> and DC<7:0> should be fixed at "L" or "H". Note : The three pieces of 256K-word x 8-bit FIFO are cascade-connected, and a line delay data can be made easily. Write and read operation of FIFO after the 2nd line is controlled by the read system pin of the 1st line.
(c) 2002 MITSUBISHI ELECTRIC CORPORATION
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MITSUBISHI
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
MODE 3 OPERATION DESCRIPTIONS

DA<7:0> WCKA WRESA WEA
8 8
256K x 8-bit FIFO(A)
QA<7:0> RCKA RRESA REA
In mode 3, two FIFO memories with 8-bit data bus are cascade-connected and the other FIFO memory with an 8-bit data bus is configured completely independently. This makes it possible to generate delay data for 2-lines without external wiring and to control the other independent one FIFO memory.
8
8
256K x 8-bit FIFO(B)
QB<7:0>
When write enable input WEA is "L", the contents of data input DA<7:0> are written into FIFO (A) in synchronization with the rising of write clock input WCKA. At this time, the write address counter of FIFO (A) is incremented. When WEA is "H", writing into FIFO (A) is disabled and the write address counter of FIFO (A) is stopped. When write reset input WRESA is "L", the write address counter of FIFO (A) is initialized. When read enable input REA is "L", the contents of FIFO (A) and FIFO (B) are outputted to each QA<7:0> and QB<7:0> in synchronization with the rising of read clock input RCKA. At this time, the read address counters of FIFO (A) and FIFO (B) are incremented.
8
DC<7:0> WCKC WRESC WEC
8
256K x 8-bit FIFO(C)
QC<7:0> RCKC RRESC REC
Also the data of FIFO (A) is written into FIFO (B) in synchronization with the rising of RCKA. At this time, the write address counter of FIFO (B) is incremented simultaneously. When REA is "H", reading from FIFO (A) and FIFO (B) is disabled and the read address counter of each FIFO is stopped. Also QA<7:0> and QB<7:0> become high impedance state. And writing into FIFO (B) is disabled and the write address counter of FIFO (B) is stopped. When read reset input RRESA is "L", the read address counter of FIFO (A) and the write address counter/read address counter of FIFO (B) are initialized. The operation of FIFO (C) is the same as that of mode 1. And, in mode 3, all pins for the A-system and C-system, and QB<7:0> are only used. Therefore the write/read control pins for the B-system and DB<7:0> should be fixed at "L" or "H". Note : The two pieces of 256K-word x 8-bit FIFO are cascade-connected and, a piece of 256K-word x 8-bit FIFO can be operated completely independently. Write and read operation of FIFO at the 2nd line is controlled by the read system pin of the 1st line.
(c) 2002 MITSUBISHI ELECTRIC CORPORATION
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MITSUBISHI
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
MODE 4 OPERATION DESCRIPTIONS

DA<7:0> DB<3:0> WCKA WRESA WEA
12 12
256K x 12-bit FIFO(A)
QA<7:0> QB<3:0> RCKA RRESA REA
In mode 4, two FIFO memories with 12-bit data bus can be controlled completely individually. Taking FIFO (A) as an example, the operation of FIFO memory is described below. The operation of FIFO (B) is the same as that of FIFO (A). When write enable input WEA is "L", the contents of data input DA<7:0> and DB<3:0>are written into FIFO (A) in synchronization with the rising of write clock input WCKA. At this time, the write address counter of FIFO (A) is incremented. When WEA is "H", writing into FIFO (A) is disabled and the write address counter of FIFO (A) is stopped. When write reset input WRESA is "L", the write address counter of FIFO (A) is initialized.
DC<7:0> DB<7:4> WCKB WRESB WEB
12
12
256K x 12-bit FIFO(B)
QC<7:0> QB<7:4> RCKB RRESB REB
When read enable input REA is "L", the contents of FIFO (A) are outputted to data output QA<7:0> and QB<3:0> in synchronization with the rising of read clock input RCKA. At this time, the read address counter of FIFO (A) is incremented. When REA is "H", reading from FIFO (A) is disabled and the read address counter of FIFO (A) is stopped. Also QA<7:0> and QB<3:0> become high impedance state. When read reset input RRESA is "L", the read address counter of FIFO (A) is initialized. Also, set the 12-bit I/O buses of FIFO (A) and FIFO (B) as shown in the table below. In mode 4, all pins for the A-system and B-system, DC<7:0> and QC<7:0> are only used. Therefore the write/read control pins for the C-system should be fixed at "L" or "H". External pin Data input External pin Data output bus of FIFO name bus of FIFO name (A) (A) DA<7> 11-bit QA<7> 11-bit DA<6> 10-bit QA<6> 10-bit DA<5> 9-bit QA<5> 9-bit DA<4> 8-bit QA<4> 8-bit DA<3> 7-bit QA<3> 7-bit DA<2> 6-bit QA<2> 6-bit DA<1> 5-bit QA<1> 5-bit DA<0> 4-bit QA<0> 4-bit DB<3> 3-bit QB<3> 3-bit DB<2> 2-bit QB<2> 2-bit DB<1> 1-bit QB<1> 1-bit DB<0> 0-bit QB<0> 0-bit External pin Data input External pin Data output bus of FIFO name bus of FIFO name (B) (B) DC<7> 11-bit QC<7> 11-bit DC<6> 10-bit QC<6> 10-bit DC<5> 9-bit QC<5> 9-bit DC<4> 8-bit QC<4> 8-bit DC<3> 7-bit QC<3> 7-bit DC<2> 6-bit QC<2> 6-bit DC<1> 5-bit QC<1> 5-bit DC<0> 4-bit QC<0> 4-bit DB<7> 3-bit QB<7> 3-bit DB<6> 2-bit QB<6> 2-bit DB<5> 1-bit QB<5> 1-bit DB<4> 0-bit QB<4> 0-bit
Note : The two pieces of 256K-word x 12-bit FIFO can be operated completely independently.
(c) 2002 MITSUBISHI ELECTRIC CORPORATION
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MITSUBISHI
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
MODE 5 OPERATION DESCRIPTIONS
DA<7:0> DB<3:0> WCKA WRESA WEA
12
12

QA<7:0> QB<3:0> RCKA RRESA REA
256K x 12-bit FIFO(A)
In mode 5, two FIFO memories with 12-bit data bus are cascade-connected and it is possible to generate delay data for 2-lines without external wiring. When write enable input WEA is "L", the contents of data input DA<7:0> and DB<3:0> are written into FIFO (A) in synchronization with the rising of write clock input WCKA. At this time, the write address counter of FIFO (A) is
12
12
256K x 12-bit FIFO(B)
QC<7:0> QB<7:4>
incremented. When WEA is "H", writing into FIFO (A) is disabled and the write address counter of FIFO (A) is stopped. When write reset input WRESA is "L", the write address counter of FIFO (A) is initialized.
When read enable input REA is "L", the contents of FIFO (A) and FIFO (B) are outputted to each QA<7:0>, QB<3:0> and QC<7:0> and QB<7:4> in synchronization with the rising of read clock input RCKA. At this time, the read address counters of FIFO (A) and FIFO (B) are incremented. Also the data of FIFO (A) is written into FIFO (B) in synchronization with the rising of RCKA. At this time, the write address counter of FIFO (B) is incremented simultaneously. When REA is "H", reading from FIFO (A) and FIFO (B) is disabled and the read address counter of each FIFO is stopped. Also all data outputs become high impedance state. And writing into FIFO (B) is disabled and the write address counter of FIFO (B) is stopped. When read reset input RRESA is "L", the read address counter of FIFO (A) and the write address counter/read address counter of FIFO (B) are initialized. Also, set the 12-bit I/O buses of FIFO (A) and FIFO (B) as shown in the table below. In mode 5, all pins for the A-system, DB<3:0>, QB<7:0> and QC<7:0> are only used. Therefore the write/read control pins for the B-system and the C-system, DB<7:4> and DC<7:0> should be fixed at "L" or "H". External pin Data input External pin Data output bus of FIFO name bus of FIFO name (A) (A) DA<7> 11-bit QA<7> 11-bit DA<6> 10-bit QA<6> 10-bit DA<5> 9-bit QA<5> 9-bit DA<4> 8-bit QA<4> 8-bit DA<3> 7-bit QA<3> 7-bit DA<2> 6-bit QA<2> 6-bit DA<1> 5-bit QA<1> 5-bit DA<0> 4-bit QA<0> 4-bit DB<3> 3-bit QB<3> 3-bit DB<2> 2-bit QB<2> 2-bit DB<1> 1-bit QB<1> 1-bit DB<0> 0-bit QB<0> 0-bit External pin Data output name bus of FIFO (B) QC<7> 11-bit QC<6> 10-bit QC<5> 9-bit QC<4> 8-bit QC<3> 7-bit QC<2> 6-bit QC<1> 5-bit QC<0> 4-bit QB<7> 3-bit QB<6> 2-bit QB<5> 1-bit QB<4> 0-bit
Note : The two pieces of 256K-word x 12-bit FIFO are cascade-connected, and a line delay data can be made easily. Write and read operation of FIFO at the 2nd line is controlled by the read system pin of the 1st line. (c) 2002 MITSUBISHI ELECTRIC CORPORATION 9
MITSUBISHI
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS (Ta = 0 ~ 70C, unless otherwise noted)
Symbol VCC18 VCCIO VI VO Pd Tstg Parameter Supply voltage (1.8 V power supply ) Supply voltage (3.3 V power supply ) Input voltage Output voltage Maximum power dissipation Storage temperature Conditions A value based on GND Ratings -0.3~+2.5 -0.3~+3.8 -0.3~VCCIO+0.3 -0.3~VCCIO+0.3 800 -55~150 Unit V V V V mW C
Ta = 70 C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC18 VCCIO Topr Parameter Supply voltage for internal circuit (1.8 V power supply ) Supply voltage for I/O (3.3 V power supply ) Operating ambient temperature Test conditions A value based on GND Min. 1.62 3.0 0 Limits Typ. 1.8 3.3 Unit Max. 1.98 3.6 70 V V C
DC CHARACTERISTICS (Ta = 0 ~ 70C, Vcc18 = 1.8 0.18 V, VccIO = 3.3 0.3 V, GND = 0 V, unless otherwise noted)
Symbol VIH VIL VOH VOL IIH IIL IOZH IOZL ICC18 ICCIO Parameter "H" input voltage "L" input voltage "H" output voltage "L" output voltage "H" input current "L" input current Off state "H" output current Off state "L" output current Operating mean current dissipation (1.8 V) Operating mean current dissipation (3.3 V) Input capacitance Off state output capacitance IOH = -4mA IOL = 4mA VI = VCCIO VI = GND VO = VCCIO VO = GND VCC18 = 1.8 V 0.18 V VCCIO = 3.3 V 0.3 V VI = repeat "H" and "L" Output open tWCK = tRCK = 16.6 ns f = 1 MHz f = 1 MHz VccIO - 0.4 0.4 10 -10 10 -10 135 145 Test conditions A value based on GND Min. 0.8 x VccIO Limits Typ. Unit Max. V 0.2 x VccIO V V V A A A A mA mA
CI CO
10 15
pF pF
(c) 2002 MITSUBISHI ELECTRIC CORPORATION
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MITSUBISHI
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
POWER - ON
After power-on, this IC initializes some circuits of internal FIFO (1.8 V), using the built-in power-on reset circuit. This power-on reset is performed by using the VCC18 = 1.8 V system power supply. Either of the following conditions (1) or (2) should be met according to the power-on time of the VCC18. (1) When the power-on time of the VCC1.8 is 1 msec or less: Some circuits of internal FIFO are initialized by the built-in power-on reset circuit. No restriction is imposed on the power-on sequence between VCC18 and VCCIO = 3.3 V system power supply. When powering on again after power-on, provide an interval of 100 ms or more for the VCC18. At this time, the TEST1 (pin 99) pin should be fixed at "L".
1ms(max) 100ms(min)
VCC18
VCC18
GND VCC18 x 10% VCC18 x 10%
(2) When the power-on time of the VCC18 is more than 1 msec: Some circuits of internal FIFO should be initialized by the TEST1 (pin 99) pin. Input a initialize reset pulse of 200 ns or more after the power supplies (VCCIO, VCC18) reach to the VCC level. There is no problem even if reaching to the VCC level on which power supply.
3.0V~3.6V
3.0V~3.6V
VCCIO
VCCIO
GND
1ms or more 1.62V~1.98V
VCC18
VCC18
GND
200ns(min)
200ns(min)
VCCIO
TEST1
GND
Note : Some circuits of internal FIFO can be initialized by the TEST1 pin even if the power-on time of the VCC18 is 1 msec or less.
Note : Important matter; Provide write reset cycles and read reset cycles of 100 cycles or more, respectively after the VCC reaches to the specified voltage after power-on. When inputting a reset pulse using the TEST1 (pin 99) pin, provide write reset cycles and read reset cycles of 100 cycles or more, respectively after inputting a reset pulse at power-on. There is no problem in this reset operation if a total of 100 cycles or more is achieved, even if discontinuous reset input is made.
(c) 2002 MITSUBISHI ELECTRIC CORPORATION
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MITSUBISHI
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
TIMING REQUIREMENTS (Ta = 0 ~ 70C, VCC18 = 1.8 0.18 V, VCCIO = 3.3 0.3 V, GND = 0 V, unless otherwise noted)
Symbol Parameter Min. t WCK t WCKH t WCKL t RCK t RCKH t RCKL t DS t DH t RESS t RESH t NRESS t NRESH t WES t WEH t NWES t NWEH t RES t REH t NRES t NREH t r, t f Write clock (WCK) cycle Write clock (WCK) "H" pulse width Write clock (WCK) "L" pulse width Read clock (RCK) cycle Read clock (RCK) "H" pulse width Read clock (RCK) "L" pulse width Input data setup time to WCK Input data hold time to WCK Reset setup time to WCK or RCK Reset hold time to WCK or RCK Reset nonselect setup time to WCK or RCK Reset nonselect hold time to WCK or RCK Write enable setup time to WCK Write enable hold time to WCK Write enable nonselect setup time to WCK Write enable nonselect hold time to WCK Read enable setup time to RCK Read enable hold time to RCK Read enable nonselect setup time to RCK Read enable nonselect hold time to RCK Input pulse rise/fall time 16.6 6.5 6.5 16.6 6.5 6.5 3.5 2 3.5 2 3.5 2 3.5 2 3.5 2 3.5 2 3.5 2 3 Limits Typ. Max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
SWITCHING CHARACTERISTICS (Ta = 0 ~ 70C, VCC18 = 1.8 0.18 V, VCCIO = 3.3 0.3 V, GND = 0 V, unless otherwise noted)
Symbol Parameter Min. t AC t OH t OEN t ODIS Output access time to RCK Output hold time to RCK Output enable time to RCK Output disable time to RCK 2 2 2 13 13 Limits Typ. Max. 13 ns ns ns ns Unit
(c) 2002 MITSUBISHI ELECTRIC CORPORATION
12
MITSUBISHI
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
SWITCHING CHARACTERISTICS MEASUREMENT CIRCUIT
Vcc IO RL=1K SW1 Qn Qn SW2 CL=10pF: tAC,tOH RL=1K CL=3pF: tOEN,tODIS
Parameter tODIS (LZ) tODIS (HZ) tOEN (ZL) tOEN (ZH) Input pulse level Decision voltage input : 0~VCCIO : 1/2 VCCIO of that for decision).
SW1 Close Open Close Open Open Close Open Close
SW2
Input pulse rise/fall time : 1 ns Decision voltage output : 1/2 VCCIO (However, tODIS (LZ) is 10% of output amplitude and tODIS (HZ) is 90% The load capacitance CL includes the floating capacitance of connection and the input capacitance of probe.
tODIS and tOEN MEASUREMENT CONDITION
VIH
RCK
1/2 VccIO
1/2 VccIO VIL
VIH
RE
VIL tODIS(HZ) 90% tOEN(ZH) VOH 1/2 VccIO
Qn
tOEN(ZL) tODIS(LZ)
Qn
10%
1/2 VccIO VOL
(c) 2002 MITSUBISHI ELECTRIC CORPORATION
13
MITSUBISHI
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
OPERATING TIMING
l WRITE CYCLE
n cycle
n+1 cycle
n+2 cycle
Disable cycle
n+3 cycle
n+4 cycle
WCK tWCK tWCKH tWCKL tWEH tNWES tNWEH tWES
WE tDS tDH Dn tDS tDH
(n)
(n+1)
(n+2)
(n+3)
(n+4)
WRES = "H"
l WRITE RESET CYCLE
n-1 cycle
n cycle
Reset cycle
0 cycle
1 cycle
WCK tWCK WRES tNRESH tRESS tRESH tNRESS
tDS tDH Dn
tDS tDH
(n-1)
(n)
(0)
(1)
In case of WE = "L"
(c) 2002 MITSUBISHI ELECTRIC CORPORATION
14
MITSUBISHI
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
WRITE RESET and WRITE ENABLE COMBINATION CYCLE
n cycle
n+1 cycle
n+2 cycle
Disable cycle
0 cycle
1 cycle
WCK tWCK tWCKH tWCKL tWEH tNWES tNWEH tWES
WE tNRESH tRESS tRESH tNRESS WRES tDS tDH Dn (n) (n+1) tDS tDH (n+2) (0) (1)
Note : There are no restrictions of WE to WRES.
(c) 2002 MITSUBISHI ELECTRIC CORPORATION
15
MITSUBISHI
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
l READ CYCLE
n cycle
n+1 cycle
n+2 cycle
Disable cycle
n+3 cycle
n+4 cycle
RCK tRCK tRCKH tRCKL tREH tNRES tNREH tRES
RE tAC (n) tOH (n+1) (n+2) tOH RRES = "H" tODIS HIGH-Z tOEN
Qn
(n+3)
(n+4)
l READ RESET CYCLE
n-1 cycle
n cycle
Reset cycle
0 cycle
1 cycle
RCK tRCK RRES tNRESH tRESS tRESH tNRESS
tAC Qn (n-1)
tAC (n) tOH
tAC (0) tOH In case of RE = "L" (1)
tOH
(c) 2002 MITSUBISHI ELECTRIC CORPORATION
16
MITSUBISHI
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
READ RESET and READ ENABLE COMBINATION CYCLE
n cycle
n+1 cycle
n+2 cycle
Disable cycle
0 cycle
1 cycle
RCK tRCK RE tNRESH tRESS tRESH tNRESS tRCKH tRCKL tREH tNRES tNREH tRES
RRES tAC Qn (n) tOH (n+1) tAC (n+2) tOH tODIS
HIGH-Z
tOEN (0)
tAC (1)
tOH
Note : There are no restrictions of RE to RRES.
(c) 2002 MITSUBISHI ELECTRIC CORPORATION
17
MITSUBISHI
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
ATTENTIONS when WCK and RCK STOP
The intervals of 16 cycles or more between a write cycle and a read cycle should be secured, and WCK and RCK should be inputted for 16 cycles or more based on beginning of write n cycle at any timing, when both WCK and RCK or either of both is stopped and the newest data is read after it restarts. Output data becomes undefined when these restrictions are not filled. When WCK and RCK stop synchronously
n cycle n+1 cycle n+2 cycle n+m-1 cycle n+m cycle n+m+1 cycle n+m+2 cycle n+m+3 cycle
WCK tDS tDH Dn
(n) (n+1) (n+2) (n+m-1) (n+m) (n+m+1) (n+m+2) (n+m+3)
m cycle
n-m cycle
n-m+1 cycle
n-m+2 cycle
n-1 cycle
n cycle
n+1 cycle
n+2 cycle
n+3 cycle
RCK tAC Qn
(n-m) (n-m+1) (n-m+2) (n-1)
tOH
(n) (n+1) (n+2) (n+3)
m 16 WRES = "H" RRES = "H" WE = "L" RE = "L"
When WCK and RCK stop asynchronously
n-1 cycle n cycle n+m cycle n+m+1 cycle n+m+2 cycle n+m+3 cycle n+m+4 cycle
WCK tDS tDH Dn
(n-1) (n) (n+m) (n+m+1) (n+m+2) (n+m+3) (n+m+4)
m cycle
Please secure m 16 interval cycles also in the timing which a write cycle and a read cycle approach most.
n cycle n+1 cycle n+2 cycle
n-m-3 cycle
n-m-2 cycle
n-m-1cycle
n-m cycle
RCK tAC Qn
(n-m-3) (n-m-2)
tOH
(n-m-1) (n-m) (n) (n+1) (n+2)
m 16 WRES = "H" RRES = "H" WE = "L" RE = "L"
(c) 2002 MITSUBISHI ELECTRIC CORPORATION
18
MITSUBISHI
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
VARIABLE LENGTH DELAY BITS
1-LINE (262144-BIT) DELAY
In read cycles, an output data is read at the (first) rising edge of RCK start the cycle. In write cycles, an input data is written at the (second) rising edge of WCK end the cycle. So 1-line delay can be made easily according to the control method of the following figure.
Reset cycle 0 cycle 1 cycle 2 cycle 262142 cycle 262143 cycle 262144 cycle (0') 262145 cycle (1') 262146 cycle (2')
WCK RCK tRESS tRESH WRES RRES tDS tDH tDS tDH
Dn
(0)
(1)
(2)
(262141)
(262142)
(262143)
(0')
(1')
(2')
262144 cycle
tAC
tOH
Qn
(0)
(1)
(2)
WE, RE = "L"
N-BIT DELAY 1 (Reset at a cycle corresponding to delay length)
0 cycle (0') 1 cycle (1') 2 cycle (2')
Reset cycle
0 cycle
1 cycle
2 cycle
n cycle
Reset cycle
WCK RCK tRESS tRESH WRES RRES tDS tDH tDS tDH tRESS tRESH
Dn
(0)
(1)
(2)
(n-1)
(n)
(0')
(1')
(2')
Delay length n
tAC
tOH
Qn
(0)
(1)
(2)
262144 n 16 WE, RE = "L"
Note : The intervals of 16 cycles or more between a write cycle and a read cycle should be secured to read data written in a certain cycle.
(c) 2002 MITSUBISHI ELECTRIC CORPORATION
19
MITSUBISHI
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
N-BIT DELAY 2 (Sliding timings of WRES and RRES at a cycle corresponding to delay length)
Reset cycle 0 cycle 1 cycle 2 cycle n-1 cycle Reset cycle n cycle 0 cycle n+1 cycle 1 cycle n+2 cycle 2 cycle n+3 cycle 3 cycle
*****Write side *****Read side
WCK RCK tRESS tRESH WRES tRESS tRESH RRES tDS tDH tDS tDH
Dn
(0)
(1)
(2)
(n-2)
(n-1)
(n)
(n+1)
(n+2)
(n+3)
Delay length n Qn
tAC
tOH
(0)
(1)
(2)
(3)
262144 n 16 WE, RE = "L"
N-BIT DELAY 3 (Sliding address by disabling RE at a cycle corresponding to delay length)
Reset cycle 0 cycle 1 cycle 2 cycle n-1 cycle n cycle 0 cycle n+1 cycle 1 cycle n+2 cycle 2 cycle n+3 cycle 3 cycle
*****Write side *****Read side
WCK RCK tRESS tRESH WRES RRES
tNREH tRES
RE tDS tDH tDS tDH
Dn
(0)
(1)
(2)
(n-2)
(n-1)
(n)
(n+1)
(n+2)
(n+3)
Delay length n Qn
tAC
tOH
(0)
(1)
(2)
(3)
262144 n 16 WE = "L"
(c) 2002 MITSUBISHI ELECTRIC CORPORATION
20
MITSUBISHI
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
SHORTEST READING of WRITTEN DATA in N CYCLE WHEN WRITE and READ OPERATED ASYNCHRONOUSLY
The intervals of 16 cycles or more between a write cycle and a read cycle should be secured and WCK and RCK should be inputted for 16 cycles or more based on beginning of write n cycle at any timing to read written data (data fetched at the rising edge of WCK shown *1 in the following figure) with n cycles on write side. On read side, n cycles should be started after the completion of n+15 cycles on write side (t 0 in the following figure). Output data becomes undefined when these restrictions are not filled.
Reference
16 cycles or more are required in WCK. n-1 cycle n cycle n+1 cycle n+14 cycle n+15 cycle n+16 cycle n+17 cycle n+18 cycle n+19 cycle
WCK
*1
Dn
(n-1)
(n)
(n+1)
(n+14)
(n+15)
(n+16)
(n+17)
(n+18)
(n+19)
16 cycles or more are required in RCK.
t0
n cycle n+1 cycle
n-1 cycle
RCK
Qn
invalid
(n)
(n+1)
LONGEST READING of WRITTEN DATA in N CYCLE : 1-LINE DELAY
Data output Qn of n cycle <1>* can be read immediately before until the start of n cycle <1>* on read side and the start of n cycle <2>* on write side over lap each other.
n cycle <1>*
0 cycle <2>*
n cycle <2>*
WCK
Dn
(n-1)<1>*
(n)<1>*
(0) <2>*
(n-1) <2>*
(n) <2>*
n cycle <0>*
0 cycle <1>*
n cycle <1>*
RCK
Qn
(n-1)<0>*
(n) <0>*
(0) <1>*
(n-1) <1>*
(n) <1>*
<0>*, <1>* and <2>* indicate a line value.
(c) 2002 MITSUBISHI ELECTRIC CORPORATION
21

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